X-Git-Url: https://defiant.homedns.org/gitweb/?p=ros_wild_thumper.git;a=blobdiff_plain;f=avr%2Fnano%2Fmain.c;h=7b62c809209859236aba3c806f27386f3c6fbe94;hp=5ba30821e26227f6e936fede523b2d80b3dd4964;hb=540df9f5842bf55260f494c985fd75e4c54fb7cb;hpb=ed122a75c49ea77b0bcf8e33e1be03e4eecd36a7;ds=sidebyside

diff --git a/avr/nano/main.c b/avr/nano/main.c
index 5ba3082..7b62c80 100644
--- a/avr/nano/main.c
+++ b/avr/nano/main.c
@@ -5,6 +5,10 @@
 #include <avr/interrupt.h>
 #include <avr/sleep.h>
 #include <util/delay.h>
+#include <util/twi.h>
+#include <avr/eeprom.h>
+#include <avr/wdt.h>
+#include <avr/pgmspace.h>
 #include "uart.h"
 
 /*
@@ -34,9 +38,9 @@
  */
 
 
-#define TWI_ACK		TWCR = (1<<TWEA) | (1<<TWINT) | (1<<TWEN) | (1<<TWIE)
-#define TWI_RESET	TWCR &= ~((1 << TWSTO) | (1 << TWEN)); TWI_ACK
-#define TWI_NAK		TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWIE)
+#define TWI_ACK   TWCR = (1<<TWINT) | (1<<TWEA) | (1<<TWEN) | (1<<TWIE)
+#define TWI_NAK   TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWIE)
+#define TWI_RESET TWCR = (1<<TWINT) | (1<<TWEA) | (1<<TWSTO) | (1<<TWEN) | (1<<TWIE);
 
 static volatile uint8_t ireg=0;
 static volatile uint8_t bootloader=0;
@@ -55,20 +59,20 @@ ISR(TWI_vect)
 {
 	static int16_t tmp16=0;
 
-	switch (TWSR & 0xF8)
+	switch(TW_STATUS)
 	{  
-		case 0x60: // start write
+		case TW_SR_SLA_ACK: // start write
 			TWI_ACK;
 			ireg = 0;
 			break;
-		case 0x80: // write
+		case TW_SR_DATA_ACK: // write
 			switch(ireg) {
 				case 0x00: // register select
 					ireg = TWDR;
 
 					if (ireg == 0x05) start_dist_fwd1=1;
 					if (ireg == 0x07) start_dist_bwd=1;
-					if (ireg == 0x09) start_dist_fwd2=1;
+					if (ireg == 0x0b) start_dist_fwd2=1;
 
 					ireg--; // because we do ireg++ below
 					TWI_ACK;
@@ -78,10 +82,10 @@ ISR(TWI_vect)
 				default:
 					TWI_NAK;
 			}
-			ireg++;
+			if (ireg < 0xff) ireg++;
 			break;
-		case 0xA8: // start read
-		case 0xB8: // read
+		case TW_ST_SLA_ACK: // start read
+		case TW_ST_DATA_ACK: // read
 			switch(ireg) {
 				case 0x01: // Distance left MSB
 					tmp16 = dist_left;
@@ -170,6 +174,9 @@ ISR(TWI_vect)
 			}
 			ireg++;
 			break;
+		case TW_SR_STOP:
+			TWI_ACK;
+			break;
 		default:
 			TWI_RESET;
 	}
@@ -289,7 +296,7 @@ int main(void) {
 
 	// I2C
 	TWAR = 0x52;
-	TWI_RESET;
+	TWI_ACK;
 
 	// Timer 1: Normal mode, Top: 0xffff, Prescaler: F_CPU/256=62500Hz
 	TCCR1A = 0x0;
@@ -299,7 +306,7 @@ int main(void) {
 	EICRA = (1 << ISC10) | (1 << ISC00);
 	PCICR = (1 << PCIE2);
 
-	printf("\r\nStart\r\n");
+	printf_P(PSTR("\r\nStart\r\n"));
 
 	set_sleep_mode(SLEEP_MODE_IDLE);
 	sei();
@@ -317,10 +324,11 @@ int main(void) {
 			case 0xff: // Magic reg that starts the bootloader
 				if (bootloader == 0xa5) {
 					cli();
-					{
-						void (*start)(void) = (void*)0x1800;
-						start();
-					}
+					// write mark to first area in eeprom
+					eeprom_write_byte((uint8_t*)0, 123);
+					eeprom_busy_wait();
+					// Use watchdog to restart
+					wdt_enable(WDTO_15MS);
 				}
 				break;
 		}